Conventional flash memory devices, otherwise known as flash electrically erasable programmable read only memories (FLASH EEPROMs), typically include a two-dimensional array of floating gate memory transistors, or "cells," formed on a semiconductor substrate. These cells are arranged into strings, known as NAND strings, to form bit lines, wherein each cell is coupled to the next cell in the string by coupling the source of one transistor to the drain of another transistor. Word lines, disposed perpendicularly to the bit lines, connect to the control gate of one transistor in each NAND string.
A portion of a flash memory circuit, including three bit lines 302, 304, and 306 and four of sixteen word lines, is depicted in FIG. 3. Each bit line, e.g. bit line 304, comprises a NAND string of floating gate transistors coupled in series source to drain, for example, transistors 310, 312, and 314 for bit line 304. FIG. 4 shows a cross-section of floating gate transistors 310, 312, and 314 on bit line 304. Floating gate transistor 312 is formed on a substrate 400, having a source region 402 (which is a drain region for neighboring transistor 314), a drain region 404 (which is a source region for neighboring transistor 310), and a doped channel region 406. A gate oxide 408 is formed on the channel region 406 to insulate the floating gate 410 from the channel region 406. An insulating layer 412 physically and electrically separates the floating gate 410 from a control gate 414, which is coupled to an appropriate word line, e.g., word line 2 for floating gate transistor 312.
Initially, the cells in a flash memory are erased so that the floating gate memory transistors are at a certain threshold voltage, such as about -2V. Selected cells are programmed by applying a high voltage, such as about 18V-23V, to the word lines of the selected cells. For example, selected cell 312 is programmed by applying a high voltage to word line 2. Applying the programming voltage causes electrons tunneling from the silicon substrate to the floating gate 410 of a selected flash memory transistor 312, thereby increasing the threshold voltage of the selected flash memory transistor 312 to a positive voltage, such as about +1V. By adjusting the threshold voltage of selected floating gate memory transistors, flash memory cells are programmed to store data.
A conventional approach for reading data from a selected memory cell involves selecting a bit line by applying a IV bias to the drain end of a selected bit line and grounding the drain ends of unselected bit lines and the source ends of both selected and unselected bit lines. A memory cell on a particular word line is selected by applying a gate voltage (V.sub.GATE) of about 0V to the word line and by applying a pass voltage (V.sub.PASS) of about 4.5V to the other word lines. The pass voltage is sufficient to cause unselected cells on the selected bit line to turn on. Referring to FIG. 3, if the floating gate transistor 312 of a selected cell has been programmed to a 1V threshold voltage, then the gate voltage V.sub.GATE =0 is insufficient to turn the floating transistor 312 on and very little drive current is produced from the selected transistor for the selected bit line indicating that the selected cell is programmed. On the other hand, if the floating gate transistor 312 of the selected cell is still at the erased threshold voltage (e.g. at -2V), then the floating gate transistor 312 is on, since the gate voltage V.sub.GATE =0 is greater than the threshold voltage (-2V). Accordingly, a drive current is produced for the selected bit line indicating that the selected cell is erased.
Escalating demands for high density and performance associated with flash memory devices challenge the limitations of conventional flash memory technology. For example, it is desirable to reduce the channel length of the floating gate transistor to pack the transistors more densely. However, merely shortening the channel length from a conventional 0.25 .mu.m to produce smaller transistors creates a "punchthrough" condition. Referring again to FIG. 4, punchthrough is a malfunction which occurs when the depletion region 420 caused by a source-drain bias extends through the entirety of the channel region 406 and short-circuits the transistor. Consequently, the transistor is always turned on and thus appears to be always erased even though it is programmed.
Furthermore, the conventional flash memory device depicted in FIG. 3 requires a 4.5V pass voltage. As lower power supply voltages, e.g. 3.3V, become more popular, however, it is desirable to use a lower pass voltage, commensurate with the power voltage, and to reduce the silicon substrate doping concentration for improved tunnel oxide integrity and product reliability. However, merely reducing the doping level of the channel region to reduce the threshold voltage for the lower pass voltage exacerbates the punchthrough problem. Consequently, conventional flash memory devices employ additional voltage boosting circuitry, such as a charge pump, to provide a 4.5V pass voltage from a 3.3V power supply. This additional circuitry increases the die size and hinders scalability.
When the pass voltage on the unselected cell in the selected bit line is increased, however, the electric field across the tunnel oxide is also increased. This electric field encourages electrons to leak into the floating gate from the silicon substrate through trap assisted tunneling processes. Since the rate of charge leakage is exponentially proportional to the electric field, a high pass voltage results in a greater occurrence of a charge gain error and impairs device reliability. Therefore, it is also desirable to lower the pass voltage to reduce the occurrence of "read disturb," an error condition in which a cell is accidentally programmed during a read operation.